1. Field of the Invention
The present invention relates to an MOS current mirror and, more particularly, to an MOS cascode current mirror arrangement which requires only a single reference current while providing a large output impedance.
2. Description of the Prior Art
Current mirror circuits are well known in the art and have found uses in a variety of applications. Generally speaking, a current mirror circuit comprises a pair of transistors where an input reference current source is connected to drive one of the transistors. The pair of transistors are connected together in a manner whereby the reference current is substantially reproduced, or mirrored, at the output of the second transistor. In most cases, the critical factor in designing a current mirror circuit is providing optimum matching between the reference and output currents. U.S. Pat. No. 4,297,646 issued to LoCascio et al on Oct. 27, 1981 relates to a current mirror circuit, comprising bipolar transistors, with improved current matching provided by utilizing a single, split collector lateral bipolar transistor.
Current mirrors can also be formed using MOS devices, where one such arrangement is disclosed in U.S. Pat. No. 4,327,321 issued to H. Suzuki et al on Apr. 27, 1982. The Suzuki et al circuit also includes a resistor in the input rail between a P-channel MOSFET and an N-channel MOSFET to minimize the output current dependency on variations in the power supply. In MOS technology, small channel length devices are increasingly in demand. In relation to current mirror circuits, the decrease in channel length results in the decrease of the output impedance of the current mirror. Cascoding techniques become necessary, therefore, to increase the output impedance.
The advantages of cascoding transistors to form a stable current mirror are further exemplified in U.S. Pat. No. 4,412,186 issued to K. Nagano on Oct. 25, 1983. Like the LoCascio arrangement, Nagano discloses a current mirror circuit comprising bipolar transistors. In the Nagano arrangement, however, the circuit includes two stages, each having three transistors of one conductivity type and a fourth of the opposite conductivity type. When the four transistors are matched, the collector-to-emitter voltages, V.sub.CE, of the third and fourth transistors are equivalent to their base-to-emitter voltages, V.sub.BE.
These and other prior art cascode current mirror arrangements have not been widely used since they often exhibit one or more of the following problems; insufficient maximum voltage swing, excessive power consumption, insufficient output impedance, and inability to incorporate into integrated circuit designs.